There are two types of memories; single clock memory and double clock memory. The single clock memory is a memory which takes in both row and column addresses in response to a single clock signal. FIG. 8 shows a typical circuit configuration of this type of a dynamic random access memory (DRAM). In the single clock memory shown in FIG. 8, row address A0 through A10 and column address A11 through A21 are applied to their respective address input terminals and entered simultaneously into a row address buffer and a column address buffer by a single clock signal -CE (negative polarity signal of CE).
On the other hand, the double clock memory is a memory which takes in both row and column addresses at different timing in address multiplexing. FIG. 9 shows a typical circuit configuration of a double clock memory DRAM. In the memory shown in FIG. 9, row and column addresses are applied sequentially to the same address input terminals A0 through A10, the row address being entered into a row address buffer by row address strobe signal -RAS (negative polarity signal of RAS), the column address being entered into a column address buffer by a column address strobe signal -CAS (negative polarity signal of CAS).
When -RAS is active (low level), the double clock DRAM latches (holds) the row address and the sense amplifier of the memory cell array latches data. A data access called page mode can now be implemented in the double clock DRAM. The page mode is a mode of accessing individual memory cells by fixing one row address provided to the DRAM, and then continuously providing different column addresses to the DRAM.
The single clock DRAM makes it a condition that row and column addresses are generated simultaneously, and the row circuits (such as the sense amplifier) and the column circuits are controlled by a single external clock. Consequently, terminating an access to a memory cell resets the row and column addresses latched in the memory. As a result, there exists a problem that the single clock DRAM cannot implement the page mode that is allowed with the double clock DRAM.
In addition, there emerges another problem that even if the single clock DRAM is given the row address holding function and data holding function, the page mode cannot be immediately performed. The page mode and the ordinary mode differ from each other in the control process within the memory. The page mode requires modification of the control process performed in the ordinary mode. That is, the page mode requires execution of the memory control process specific to each phase or state of the page mode, such as "start of page mode," "during-page mode" and "end of page mode." So it requires identifying these operation states. The simplest method for identifying the operation mode states is to use two bits to identify the above states but this method requires the addition of two external control lines, and is not preferable.